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硬件中断机制

日期:2015-07-18 20:51:57
  
最后更新日期:2015-07-18 21:33:18
1.X86(80386)中断系统图
AT机上的中断控制芯片8259A,《微机原理》有详细介绍。通过编程控制中断向量号,早期16位cpu,中断函数入口地址为cs:pos,占用4个字节,中断向量表全部放在内存的低1k内。8259A具体的设置方法也就是向相应的端口,发送设置命令。32位保护模式下用中断描述符表来代替中断向量表。当然,中断向量号还是一样的。这种代替可以让中断例程的代码位于32位的基地址的段内,并且偏移也是32位的。图中的8259A是级联的,一块8259A芯片有个8个引脚,两块级联时,其中一块芯片的一个引脚提供给另外一个芯片,故只有15个中断引脚供外设使用。

2.高级中断控制器APIC(Advanced Programmable Interrupt Controller)
图片和英文叙述来源于-IA-32卷3 chapter 10
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Individual pins on the I/O APIC can be programmed to generate a specific interrupt vector when asserted. The I/O
APIC also has a “virtual wire mode” that allows it to communicate with a standard 8259A-style external interrupt
controller. Note that the local APIC can be disabled (see Section 10.4.3, “Enabling or Disabling the Local APIC”).
This allows an associated processor core to receive interrupts directly from an 8259A interrupt controller.
Both the local APIC and the I/O APIC are designed to operate in MP systems (see Figures 10-2 and 10-3). Each
local APIC handles interrupts from the I/O APIC, IPIs from processors on the system bus, and self-generated interrupts.
Interrupts can also be delivered to the individual processors through the local interrupt pins; however, this
mechanism is commonly not used in MP systems.
------ 原文引用 end------
local APIC and the I/O APIC机制设计是适应多核时代,I/O APIC有个virtual wire mode模式,可以直接与8259A控制器相连,同时CPU也可以禁止local APIC功能,从而直接接收8259A芯片信号,这样就兼容早期架构了。看上诉架构图,I/O APIC的封装中断信号为中断信息发往总线,其中一个cpu的local APIC读到该中断信息,处理中断例程。